1. Field of the Invention
Apparatuses and methods consistent with the present invention relate to a micro package, a multi-stack micro package and a manufacturing method therefor, and more particularly to a micro package, a multi-stack micro package and a manufacturing method therefor capable of guaranteeing hermitical sealing of a package and preventing damages to inside devices of the package.
2. Description of the Related Art
A today's trend in electronics industries is to manufacture light-weighted, compact, high-speed, multi-function, and high-performance products at low cost together with high reliability. The package assembly technologies are one kind of important technologies enabling the design goal of such products to be achieved. The chip scale package or the chip size package is a new type of package recently developed and proposed, which has many advantages compared to typical plastic packages. The most highlighted advantage of the chip scale package is the package size itself. According to the definition by the international semiconductor associations such as the Joint Electron Device Engineering Council (JEDEC) and the Electronic Industry Association of Japan (ETAJ), the chip scale package has a package size smaller than 1.2 times a chip size.
The chip scale package is mainly used for products requiring compactness and mobility, such as digital camcorders, hand-held phones, notebook computers, memory cards, and so on. A semiconductor device such as a digital signal processor (DSP), an application specific integrated circuit (ASIC), a micro controller is built in a chip scale package. Further, the chip scale package is being widely used which mounts therein a memory device such as a dynamic random access memory (DRAM), a flash memory, and so on. Currently, various chip scale packages over 50 types are being developed or have been produced across the world.
FIG. 1 is a cross-sectional view for showing a micro gap wafer-level package disclosed in U.S. Pat. No. 6,376,280. In FIG. 1, the micro gap wafer-level package 10 has a base wafer 12 connected to the micro device 14 being an active device such as an integrated circuit or a passive device such as a sensor. Further, bonding pads 16 and 18, electrically connected to the micro device 14 by conductive leads (not shown), are also associated with the base wafer 12. Around the perimeter of the base wafer 12 is a peripheral pad 20 which may be deposited at the same time as the bonding pads 16 and 18.
A peripheral pad seal, that is, a gasket 22 is extended between a cap wafer 24 and the peripheral pad 20 on the base wafer 12 and is cold weld bonded to the peripheral pad 20 to provide a hermetically sealed volume 25 around the micro device 14. The cap wafer 24 can be made of an electronically non-conductive material or a high-resistivity semiconductor material, such as single crystal silicon. However, the base wafer 12 and the cap wafer 24 are made of the same semiconductor material to avoid thermal expansion mismatch problems.
The cap wafer 24 has through holes 26 and 28 provided therein to allow access to the bonding pads 16 and 18, respectively. Conductors, such as bonding wires 30 and 32 can be respectively wire bonded to the bonding pads 16 and 18 to make the electrical connections to the micro device 14. The gaskets 34 and 36 are bonded to the peripheral pad 20 to form a hermetically sealed volume 25. The hermetically sealed volume 25 encompasses the micro device 14 and the bonding pad gaskets 34 and 36.
However, the micro gap wafer-level package disclosed in the U.S. Pat. No. 6,376,280 has a problem of increasing parasitic capacitance and insertion loss due to wire bonding. Further, there exist problems of limitation on chip size reduction due to formation of the pads and damages to the inside of a package due to a process temperature increased over 350° C. Further, there exist problems of lowering productivity and cost increase due to the wire bonding.